The fabrication of integrated circuits on semiconductor wafers is a well known but complicated process. A semiconductor wafer, such as made of silicon, undergoes many process steps in order to achieve active and passive circuit elements having predefined electrical characteristics. By and large, the electrical characteristics of the integrated circuit components are a function of parameters such as processing time, chemical composition, temperature, pressure etc., all of which can be purposefully varied to achieve different electrical operating characteristics. On the other hand, process variables can change unintentionally during wafer processing, thereby altering the electrical circuit parameters, often in an undesired manner.
In order to ascertain variations of electrical circuit characteristics at different locations on the semiconductor wafer, as a function of process variables, it is a well known technique to form test cells or test structures at different locations on the wafer. Typically, a wafer is processed to produce a large number of identical circuits, each termed "die." In addition, one or more die locations can be replaced by the test cells so that after processing is complete, the test cells can be tested to determine the variance in electrical characteristics. By noting the variations in electrical characteristics over the surface of the wafer, it can then be determined what process variations occurred so that remedial action can be taken.
After wafer processing has been completed, and before separating the wafer into the individual die, the wafer generally undergoes sample testing of various die locations to determine the statistical probability that a majority of the circuits are operable. The wafer is then cut into the individual die, which die are . connected to a lead frame and encapsulated to produce a packaged device. At the packaged level, each device is completely tested to assure that its electrical operation comports with predefined specifications.
Heretofore, the results of testing the test cells were utilized to maintain accurate control over the various processing variables. The actual test of the circuit die is generally carried out on a go, no-go basis. With such test circuits and procedures, it was difficult, if not impossible, to conduct tests to determine long term reliability of the circuits.
In the field of ferroelectric components, such as capacitors, there are electrical parameters which do not generally have counterparts in conventional integrated circuit analog and digital circuits. For example, ferroelectric materials can exhibit a fatigue parameter and an aging parameter which limit the useful life of such components. Ferroelectric materials commonly employed in fabricating ferroelectric type capacitors exhibit a capacitance, as well as a hysteresis characteristic. A ferroelectric capacitor can be polarized by the application of an electric field thereacross in one direction, and polarized in a different state with an opposite electric field. As the number of polarization state changes increase over the life of the capacitor, the remanent polarization thereof tends to degrade. This is termed ferroelectric capacitor "fatigue." In addition, while a ferroelectric capacitor can store a polarized state in a non-volatile manner over a long period of time, the remanent polarization tends to decrease with time and is therefore susceptible to "aging."
From the foregoing, it can be seen that a need exists for a test structure for use with ferroelectric components to ascertain characteristics unique to such type of components. Another need exists for a ferroelectric test structure whose parameters can be determined at the wafer level, the die level as well as the packaged device level.